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New Product
SIP21106/7/8
Vishay Siliconix
150-mA Low Noise, Low Dropout Regulator
APPLICATIONS
* * * * * * Cellular Phones, Wireless Handsets PDAs MP3 Players Digital Cameras Pagers Wireless Modem
FEATURES * TSC75-6L Package (1.6 x 1.6 x 0.6 mm), and
TSOT23-5L Package Options * 1.0 % Output Voltage Accuracy at 25 C RoHS COMPLIANT * Low Dropout Voltage: 135 mV at 150 mA * SIP21106 Low Noise: 60 V(rms) (10 Hz to 100 kHz Bandwidth) With 10 nF Over Full Load Range * 35 A (typical) Ground Current at 1 mA Load * 1 A Maximum Shutdown Current at 85 C * Output Auto Discharge at Shutdown Mode * Built-in Short Circuit (330 mA typical) and Thermal Protection (160 C typical) * SiP21108 Adjustable Output Voltage * SiP21107 POK Error Flag * - 40 C to + 125 C Junction Temperature Range for Operation * Uses Low ESR Ceramic Capacitors * Fixed Voltage Output 1.3 V to 5 V in 50 mV Steps
* Noise-Sensitive Electronic Systems DESCRIPTION
The SIP21106 BiCMOS 150 mA low noise LDO voltage regulators are the perfect choice for low battery operated low powered applications. An Ultra low ground current and low dropout voltage of 135 mV at 150 mA load helps to extend battery life for portable electronics. Systems requiring a quiet voltage source, such as RF applications, will benefit from the SIP21106 low output noise. The SiP21107 do not require a noise bypass cpacitor and provides an error flag pin (POK or Power OK). POK output requires an external pull-up resistor and goes low when the supply has not come up to voltage. The SiP21108 output is adjusted with an external resistor network. The SIP21106/7/8 regulators allow stable operation with very small ceramic output capacitors, reducing board space and component cost. They are designed to maintain regulation while delivering 330 mA peak current upon turn-on. During start-up, an active pull-down circuit improves the output transient response and regulation. In shutdown mode, the output automatically discharges to ground through a 100 NMOS. The SIP21106/7/8 are available in TSOT23-5L and a super thin lead (Pb)-free TSC75-6L packages for operation over the industrial operation range (- 40 C to 85 C).
TYPICAL APPLICATION CIRCUIT
VIN C IN = 1 F
1
VIN
VOUT
5
VOUT C OUT = 1 F
EN
1
EN
BP
6 C Bypass = 10 nF
2
GND SIP21106
2
GND SIP21106
NC
5
EN
3
EN
BP
4 C Bypass = 10 nF
VIN C IN = 1 F
3
VIN
VOUT
4
VOUT COUT = 1 F
TSOT23-5L Package
TSC75-6L Package
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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VIN
1 CIN = 1 F 2
VIN
VOUT
5
VOUT COUT = 1 F EN 1 EN POK 6 POK
GND SiP21107 2 4 POK VIN CIN = 1 F TSOT23-5L Package TSC75L-6 Package 3 VIN GND SiP21107 VOUT 4 VOUT C OUT =1 F NC 5
EN
3
EN
POK
VIN C IN = 1 F
1
VIN
VOUT
5
COUT = 1 F
VOUT
EN
1
EN
Adj
6
2
GND SiP21108
2
GND SiP21108
NC
5
EN
3
EN
Adj
4
VIN CIN = 1 F
3
VIN
VOUT
4
VOUT C OUT = 1 F
TSOT23-5L Package
TSC75-6L Package
ABSOLUTE MAXIMUM RATINGS
Parameter Input Voltage, VIN to GND VEN (See Detailed Description) Output Current (IOUT) Output Voltage (VOUT) TSC75-6L Package Power Dissipation (PD)a Package Thermal Resistance (JA)b Maximum Junction Temperature, TJ(max) Storage Temperature, TSTG Lead Temperature, TL
c
Limit - 0.3 to 6 - 0.3 to 6 Short Circuit Protected - 0.3 to VIN + 0.3 TSOT23-5L 440 180 125 - 65 to 150 260 420 131
Unit V
V
mW C/W
C
Notes: a. Derate 7.6 mW/C for TSC75-6L package and 5.5 mW/C for TSOT23-5L package above TA = 70 C. b. Device mounted with all leads soldered or welded to PC board. c. Soldering for 5 sec.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter Input Voltage, VIN Operating Ambient Temperature TA Limit 2.2 to 5.5 - 40 to 85 Unit V C
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified VIN = VOUT(nom) + 1.0 V = VEN IOUT = 1 mA, CIN = 1 F, COUT = 1 F - 40 C < TA < 85 C for full
Parameter Input Voltage Range Output Voltage Accuracy Line Regulation
Symbol VIN VOUT
Tempa Full Room Full Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room
Minb Typc Maxb 2.2 - 1.0 - 2.5 - 0.2 0.006 - 0.4 45 55 90 106 135 160 45 55 90 106 135 160 35 39 180 220 75 85 75 85 60 250 300 5.5 1.0 2.5 0.2 0.4
Unit V % %/V
IOUT = 1 mA All others For 4.6 V to 5.0 V IOUT = 50 mA
Dropout Voltaged (2.2 V VOUT(nom) < 2.6 V)
VDO
IOUT = 100 mA IOUT = 150 mA IOUT = 50 mA
mV
Dropout Voltage (VOUT(nom) 2.6 V)
VDO
IOUT = 100 mA IOUT = 150 mA IOUT = 1 mA
mV
Ground Pin Currente
IGND IOUT = 150 mA SIP21106 VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, 1 mA < IOUT < 150 mA, CBP = 0.01 F SiP21107/8 VOUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, 1 mA < IOUT < 150 mA f = 1 kHz IOUT = 150 mA f = 10 kHz f = 100 kHz VOUT 2.6 V, IOUT : 1 mA to 150 mA VOUT < 2.6 V, IOUT : 1 mA to 150 mA VOUT = 2 V
A
V
Output Noise Voltagef (RMS)
eN
Room Room Room Room Room Room Room Room Room
350 70 55 25 0.003 0.006
V
Ripple Rejection
PSRR
dB
Load Regulation
LDR
%/mA 0.005 0.009 100 160 20 170 1.2 0.009 70 330 0.02 600 1 5.5 0.4 C mA A V A s
Auto Discharge Resistance Thermal Shutdown Junction Temperature Thermal Hysteresis Output Current Limit Shutdown Supply Current EN Pin Input Voltage EN Pin Input Current Output Voltage Turn-On Time
RDIS TJ(S/D) THYST IO_LIMIT ICC(off) VENH VENL IEN ton
VOUT = 0 V VEN = 0 V High = Regulator ON (Rising) Low = Regulator OFF (Falling) EN to VOUT delay; IOUT = 1 mA
Room Full Full Full Room
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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New Product
SIP21106/7/8
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified VIN = VOUT(nom) + 1.0 V IOUT = 1 mA, CIN = 1 F, COUT = 1 F - 40 C < TA < 85 C for full
Parameter
Symbol
Tempa
Minb Typc Maxb 1.2 1.212 1.230 1 0.4 90 1.5 96
Unit
Adjustable Voltage Section (SiP21108 Version only) Feedback Voltage Error Flag Section (SiP21107 Version only) POK(OFF) Leakage POK(ON) Voltage POK Thresholdg POK Hysteresis IOFF VPOKL VPOKLH VHYST RPU to VOUT or VIN ISINK = 0.5 mA VIN rising, IOUT = 1 mA, POK goes high VIN falling, IOUT = 1 mA, POK goes low Full Full Full Room A V % VAdj Room 1.188 Full 1.170 V
Notes: a. Room = 25 C, Full = - 40 to 85 C. Derate 7.6 mW/C for TSC75 and 5.5 mW/C for SOT23 above TA = 70 C b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement. e. Ground current is specified for normal operation as well as "drop-out" operation. f. Output noise is proportional to output voltage. Use formula eN = 60 V(rms)*VOUT/2.8 V. g. POK threshold percentage is calculated by VIN/VOUT x 100 %.
TIMING WAVEFORMS
VIN VEN tr 0V 1 s
tON VNOM 0.95 VNOM
VOUT
Figure 1.
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
PIN CONFIGURATION
EN BP/Adj/POK BP/Adj/POK 6 GND NC NC 5 1 2 3 GND EN
VIN TOP VIEW
VOUT
VOUT
4
VIN
TSC75-6L PACKAGE (1.6 x 1.6 x 0.6 mm)
BOTTOM VIEW
VIN GND EN
1 2 3
5
VOUT
VOUT
5
1 2
VIN GND EN
4
BP/Adj/POK
BP/Adj/POK
4
3
TOP VIEW TSOT23-5L Package Figure 2.
BOTTOM VIEW
PIN DESCRIPTION
Pin Number TSC75-6L 1 2 3 4 5 Pin Number TSOT23-5L 3 2 1 5 Name EN GND VIN VOUT NC Function By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to VIN if unused. Do not leave floating. Ground pin. For better thermal capability, directly connected to large ground plane. Input supply pin. Bypass this pin with a 1 F ceramic or tantalum capacitor to ground. Output voltage. Connect COUT between this pin and ground. No Connection. - BP (SIP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor should be connected from this pin to ground. - Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output voltage for trim value of 1.2005 V. - POK (SiP21107): Power OK (Error Flag) pin. Open-drain output, which requires connecting a pull-up resistor to VIN or VOUT. POK pin is actively high to indicate an output normal operation condition on regulator and goes low to indicate under-voltage fault condition.
6
4
BP/Adj/POK
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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SIP21106/7/8
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ORDERING INFORMATION
Part Number SiP21108DVP-T1-E3 SIP21106DVP-18-E3 SIP21106DVP-25-E3 SIP21106DVP-26-E3 SIP21106DVP-28-E3 SIP21106DVP-30-E3 SIP21106DVP-33-E3 SIP21106DVP-46-E3 SIP21106DVP-285-E3 SiP21107DVP-18-E3 SiP21107DVP-25-E3 SiP21107DVP-26-E3 SiP21107DVP-28-E3 SiP21107DVP-30-E3 SiP21107DVP-33-E3 SiP21107DVP-46-E3 SiP21107DVP-285-E3 SiP21108DT-T1-E3 SIP21106DT-18-E3 SIP21106DT-25-E3 SIP21106DT-26-E3 SIP21106DT-28-E3 SIP21106DT-285-E3 SIP21106DT-30-E3 SIP21106DT-33-E3 SIP21106DT-46-E3 SiP21107DT-18-E3 SiP21107DT-25-E3 SiP21107DT-26-E3 SiP21107DT-28-E3 SiP21107DT-285-E3 SiP21107DT-30-E3 SiP21107DT-33-E3 SiP21107DT-46-E3 Marking AA BG BP BR BT BV BY CM CT DG DP DR DT DV DY EM ET N9 N1 NA NC N2 NE NG N3 N4 N5 NB ND N6 NF NH N7 N8 Voltage Adjustable 1.8 2.5 2.6 2.8 3.0 3.3 4.6 2.85 1.8 2.5 2.6 2.8 3.0 3.3 4.6 2.85 Adjustable 1.8 2.5 2.6 2.8 2.85 3.0 3.3 4.6 1.8 2.5 2.6 2.8 2.85 3.0 3.3 4.6 Temperature Range Package
- 40 C to 85 C
TSC75-6L
- 40 C to 85 C
TSOT23-5L
Note: Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details.
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
TYPICAL CHARACTERISTICS
3.00 2.50 2.00 V OUT (V) I OUT = 0 mA 1.50 I OUT = 150 mA 1.00 0.50 SIP21106: 2.8 V 0.00 0.00 1.00 2.00 3.00 4.00 5.00 Deviation (%)
1.00
0.50
0.00
I OUT = 1 mA
- 0.50
- 1.00 SIP21106: 2.8 V - 1.50 - 40 - 15 10 35 60 85
VIN (V)
Temperature (C)
Output Voltage vs. Input Voltage
Output Voltage Accuracy vs. Temperature
180 160 140 120 V DO (mV) 100 80 60 40 20 SIP21106: 2.8 V 0 0 25 50 75 100 125 150 TA = - 40 C TA = + 85 C TA = + 25 C V DO (mV)
180 SIP21106: 2.8 V 160 IOUT = 150 mA 140 120 100 80 60 2 2.5 3 3.5 VOUT (V) 4 4.5 5
IOUT = 100 mA
IOUT (mA)
Dropout Voltage vs. Load Current
Dropout Voltage vs. Output Voltage
180 160 I OUT = 150 mA 140 V DO (mV) 120 100 80 60 40 SIP21106: 2.8 V 20 I OUT = 100 mA
41 40 39 38 37 36 I OUT = 50 mA 35 SIP21106: 2.8 V 34 - 15 10 35 60 85 - 40 - 15 10 35 60 85 Temperature (C) Temperature (C) I OUT = 1 mA I OUT = 150 mA
- 40
Dropout Voltage vs. Temperature
Ground Current vs. Temperature
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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SIP21106/7/8
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TYPICAL CHARACTERISTICS
50 VIN = 5.5 V 45 VIN = 3.8 V I GND (A) I GND (A) 40 30 IOUT = 1 mA 40 IOUT = 150 mA
50
35
20
30 SIP21106: 2.8 V 25 0 25 50 75 I OUT (mA) 100 125 150
10 SIP21106: 2.8 V 0 0.0 1.0 2.0 3.0 VIN (V) 4.0 5.0
Ground Current vs. Output Current
Ground Current vs. Input Voltage at 25 C
80 70 60 50 PSRR (dB) 40 30 20 10 IOUT = 150 mA SIP21106: 2.8 V VIN = 3.8 V VOUT = 3.0 V CIN = 1 F COUT = 1 F IOUT = 0 mA IOUT = 100 mA CBP = 10 nF
2.820 SIP21106: 2.8 V VIN = 3.8 V 2.800 IOUT = 1 mA
V OUT (V)
2.780 IOUT = 50 mA 2.760 IOUT = 150 mA 2.740
0
-10 0.01K 0.1K 1K 10K 100K 1000K 2.720 - 40 - 15 10 35 60 85 Frequency (Hz) Temperature (C)
PSRR
Output Voltage Accuracy vs. Load Current
400 SIP21106: 2.8 V 350 300
Output Noise (V)
250 200 150 100 50 0 0.001 0.0056 0.01 0.056 0.1
BP Capacitance (F)
Output Noise vs. BP Capacitance
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
IOUT (100 mA/DIV)
IOUT (100 mA/DIV)
VOUT (50 mV/DIV) SIP21106: 4.6 V VIN = 5.5 V VOUT = 4.6 V CIN = 1 F COUT = 1 F CBP = 10 nF
VOUT (50 mV/DIV) SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF
50 S/DIV Load Transient Response
50 S/DIV Load Transient Response
SIP21106: 4.6 V VIN = 5.0 to 5.5 V VOUT = 4.6 V IOUT = 150 mA CIN = 1 F COUT = 1 F CBP = 10 nF AC Coupling VIN (200 mV/DIV)
SIP21106: 2.8 V VIN = 3.8 to 4.8 V VOUT = 2.8 V IOUT = 150 mA CIN = 1 F COUT = 1 F CBP = 10 nF VIN (1 V/DIV) AC Coupling
VOUT (10 mV/DIV) VOUT (10 mV/DIV)
200 S/DIV Line Transient Response
200 S/DIV Line Transient Response
SIP21106: 2.8 V VIN = 3.8 to 4.8 V VOUT = 2.8 V IOUT = 1 mA CIN = 1 F COUT = 1 F CBP = 10 nF VIN (1 V/DIV) AC Coupling
SIP21106: 4.6 V VIN = 5.0 to 5.5 V VOUT = 4.6 V IOUT = 1 mA CIN = 1 F COUT = 1 F CBP = 10 nF AC Coupling VIN (200 mV/DIV)
VOUT (10 mV/DIV)
VOUT (10 mV/DIV)
200 S/DIV Line Transient Response Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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SIP21106/7/8
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TYPICAL OPERATING WAVEFORMS
SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F
CBP = 10 nF
IOUT (100 mA/DIV) IOUT (50 mA/DIV)
50 mS/DIV Output Short Circuit Current
50 mS/DIV Output Short Thermal Cycling
SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF IOUT = 150 mA
VEN (1 V/DIV) VEN (500 mV/DIV)
SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF IOUT = 150 mA
VOUT (500 mV/DIV) VOUT (500 mV/DIV)
20 S/DIV Output Voltage Power-Down
20 S/DIV Output Voltage Start-Up
TYPICAL WAVEFORMS
1
Noise Spectral Density (V/Hz)
0.1
SIP21106: 2.8 V VIN = 3.8 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF IOUT = 100 mA
VOUT (100 V/DIV) VNOISE = 60 VRMS
SIP21106: 2.8 V VIN = 4.5 V VOUT = 2.8 V CIN = 1 F COUT = 1 F CBP = 10 nF IOUT = 150 mA
0.01
2 ms/DIV Output Noise
10
100
1K
10K
100K
1M
Frequency (Hz)
Output Noise Spectral Density
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
Enable Error-Amp Bandgap Reference Current Limit & Thermal VOUT
* ** *** BP/Adj/POK
POK Ref
SIP21106: BP SiP21107: POK SiP21108: Adj * SIP21106: BP *** SiP21107: POK ** SiP21108: Adj
Figure 3.
GND
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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DETAILED DESCRIPTION
As shown in the block diagram, the circuit consists of a bandgap reference, error amplifier, P-Channel pass transistor and an internal feedback resistor voltage divider, which is used to monitor and control the output voltage. A constant 1.2 V bandgap reference voltage is applied to the non-inverting input of the error amplifier. The error amplifier compares this reference with the feedback voltage on its inverting input and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled low. This increases the PMOS's gate to source voltage and allows more current to pass through the transistor to the output which increases the output voltage. Conversely, if the feedback voltage is higher than the reference voltage, the pass transistor gate is pulled high, decreasing the gate-to-source voltage, thereby allowing less current to pass to the output and causing it to drop.
Output Voltage Selection
The SIP21106 has fixed voltage outputs that are preset to voltages from 1.8 V to 4.6 V (see Ordering Information).
VIN 1.2 V Reference
+
Error-Amp VOUT
R1
R2
Figure 4.
Internal P-Channel Pass Transistor
A 0.9 (typical) P-Channel MOSFET is used as the pass transistor for the SIP21106/7/8 part series. The MOSFET transistor offers many advantages over the more, formerly, common PNP pass transistor designs, which ultimately result in longer battery lifetime. The main disadvantage of PNP pass transistors is that they require a certain base current to stay on, which significantly increases under heavy load conditions. In addition, during dropout, when the pass transistor saturates, the PNP regulators waste considerable current. In contrast, P-Channel MOSFETS require virtually zero-base drive and do not suffer from the stated problems. These savings in base drive current translate to lower quiescent current which is typical around 35 A as shown in the Typical Characteristics.
The SiP21108 has a user-adjustable output that can be set through the resistor feedback network consisting of R1 and R2. R2 range of 100K to 400K is recommended to be consistent with ground current specification. R1 can then be determined by the following equation:
R1 = R 2 x (
VOUT - 1) V ref
Where Vref is typically 1.2005 V. Use 1 % or better resistors for better output voltage accuracy (see Figure 4).
Current Limit
The SIP21106/7/8 include a current limit block which monitors the current passing through the pass transistor through a current mirror and controls the gate voltage of the MOSFET, limiting the output current to 330 mA (typical). This current limit feature allows for the output to be shorted to ground for an indefinite amount of time without damaging the device.
Shutdown and Auto-Dischage/No-Discharge
Bringing the EN voltage low will place the part in shutdown mode where the device output enters a high-impedance state and the quiescent current is reduced to below 1 A, reducing the drain on the battery in standby mode and increasing standby time. Connect EN pin to input for normal operation. The output has an internal pull down to discharge the output to ground when the EN pin is low. The internal pull down is a 100 typical resistor, which can discharge a 1 F in less than 1 ms. Refer to Typical Operating Waveforms for turn-off waveforms.
Thermal-Overload Protection
The thermal overload protection limits the total power dissipation and protects the device from being damaged. When the junction temperature exceeds TJ = 150 C, the device turns the P-Channel pass transistor off allowing the device to cool down. Once the temperature drops by about 20 C, the thermal sensor turns the pass transistor on again and resumes normal operation. Consequently, a continuous thermal overload condition will result in a pulsed output. It is generally recommended to not exceed the junction temperature rating of 125 C for continuous operation.
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Document Number: 74442 S-70067-Rev. B, 22-Jan-07
New Product
SIP21106/7/8
Vishay Siliconix
Noise Reduction in SIP21106
For the SIP21106, an external 10 nF bypass capacitor at BP pin is used to create a low pass filter for noise reduction. The startup time is fast, since a power-on circuit pre-charges the bypass capacitor. After the power-up sequence the precharge circuit is switched to standby mode in order to save current. It is therefore not recommended to use larger bypass capacitor values than 50 nF. When the circuit is used without a capacitor, stable operation is guaranteed.
Operating Region and Power Dissipation
An important consideration when designing power supplies is the maximum allowable power dissipation of a part. The maximum power dissipation in any application is dependant on the maximum junction temperature, TJ(max) = 125 C, the ambient temperature, TA, and the junction-to-ambient thermal resistance for the package, which is the summation of J-C, the thermal resistance of the package, and C-A , the thermal resistance through the PC board and copper traces. Power dissipation may be formulaically expressed as:
POK Status in SiP21107
The POK comparator monitors the output until the supply comes up to specified percentage of VIN. This open drain NMOS output requires an external pull-up resistor to either VOUT or VIN. The internal NMOS can drive up to 0.5 mA loads. POK pin is actively high to indicate an output normal operation condition on regulator and goes low to indicate under-voltage on regulator.
P(max) =
TJ (max) - TA J-C + C-A
APPLICATION INFORMATION Input/Output Capacitor Selection and Regulator Stability
It is recommended that a low ESR 1 F capacitor be used on the SIP21106/7/8 input. A larger input capacitance with lower ESR would improve noise rejection and line-transient response. A larger input bypass capacitor may be required in applications involving long inductive traces between the source and LDO. The circuit is stable with only a small output capacitor equal to 6 nF/mA ( 1 F at 150 mA) of load. Since the bandwidth of the error amplifier is around 1 - 3 MHz and the dominant pole is at the output node, the capacitor should be capacitive in this range, i.e., for 150 mA load current, an ESR < 0.4 is necessary. Parasitic inductance of about 10 nH can be tolerated. Applying a larger output capacitor would increase power supply rejection and improve loadtransient response. Some ceramic dielectrics such as the Z5U and Y5V exhibit large capacitance and ESR variation over temperature. If such capacitors are used, a 2.2 F or larger value may be needed to ensure stability over the industrial temperature range. If using higher quality ceramic capacitors, such as those with X7R and Y7R dielectrics, a 1 F capacitor will be sufficient at all operating temperatures.
The GND pin of the SIP21106/7/8 acts as both the electrical connection to GND as well as a path for channeling away heat. Connect this pin to a GND plane to maximize heat dissipation.Once maximum powChanneler dissipation is calculated using the equation above, the maximum allowable output current for any input/output potential can be calculated as
IOUT(max) =
P (max) V IN - V OUT
PCB Layout
The component placement around the LDO should be done carefully to achieve good dynamic line and load response. The input and noise capacitor should be kept close to the LDO. The rise in junction temperature depends on how efficiently the heat is carried away from junction-to-ambient. The junction-to-lead thermal impedance is a characteristic of the package and is fixed. The thermal impedance between leadto-ambient can be reduced by increasing the copper area on PCB. Increase the input, output and ground trace area to reduce the junction-to-ambient thermal impedance.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?74442.
Document Number: 74442 S-70067-Rev. B, 22-Jan-07
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